HDK Technical Reference

Bus-master devices

Bus-master devices are typically controllers that are equipped with their own processor and on-board programming necessary to carry out much of their operations, without requiring processing from the main system CPU. These bus-master devices have the intelligence necessary to move data to and from system memory without the aid of the CPU or the need to program the DMA controller with the starting address and size of transfer. This capability is very useful and is now frequently designed into high data volume devices such as SCSI controllers and network cards.

Every bus transfer has two participants: the initiator and the target. The initiator, or bus master, is the device (or, in PCI parlance, the function) that initiates a transfer. Support for bus mastering is determined by the specific hardware being used. Both EISA and PCI allow devices to initiate a bus transfer, therby becoming a bus mastering device, but not all all EISA and PCI cards and busses support bus mastering. For example, a bus-mastering capable PCI card might be installed in a bus or slot or system that does not support bus mastering. This was common for early PCI machines that only had a few bus master capable slots. To handle this, a bit in the PCI command register in the configuration header (see pci(D5)) identifies hardware (machine, bridge, and slot) that is capable of being a bus master. The driver for a card can query this bit; if it is not set, the hardware does not support bus mastering and the driver should not use it.

Drivers can use the SCO OpenServer 5 pci_read(D3oddi) functions or the SVR5 cm_read_devconfig(D3) and related functions to read the bus mastering bit in the command register. Drivers can read this bit and, if it is not set, either issue an error message or use a different I/O scheme.

Data transfer to and from the device often involves identifying the physical memory location, size and direction of transfer to the hardware. This means that it is not possible to use a buffer in user space for such transfers without some kernel help to convert from virtual to physical addresses. The bus-master device interrupts the CPU after data transfer is completed.

To verify that a PCI device really is the master, use a logic analyzer to watch the device assert its REQ# line to the arbiter and the arbiter assert the GNT# line in response. As soon as the current master releases control of the bus by deasserting FRAME# and IRDY#, it becomes the bus master.

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OpenServer 6 and UnixWare (SVR5) HDK - June 2005