HDK Technical Reference


NOTE: This article needs to be updated to reflect hardware developments in the last few years. The existing information is accurate but old and does not reflect the SCO OpenServer 5 implementation.

An interrupt is any service request that causes the CPU to stop its current execution stream and to execute an instruction stream that services the interrupt. When the CPU finishes servicing the interrupt, it returns to the original execution stream at the point where it left off.

Interrupts can be requested from any of the following sources:

Hardware devices use interrupt requests to signal a range of conditions, including device connections, data availability, error conditions, and the completion of device I/O requests. The CPU is responsible for associating an interrupt request with the proper device driver intr(D2) routine based on entries in interrupt vector tables.

NOTE: The examples and the material in this topic have been explained in terms of common Intel x86-based systems equipped with Intel's 8259 Programmable Interrupt controller. However, SVR5 is able to offer transparently similar functionality on machines with advanced interrupt controllers such as APIC, where the scope and implementation details are correctly hidden and provided through standard DDI routines.

The specific needs of interrupt handling routines for driver interfaces are discussed on the intr(D2), intr(D2oddi), intr(D2sdi), intr(D2osdi), and intr(D2mdi) manual pages. See also ``Interrupt sharing''. For information about configuring interrupt handlers on SCO OpenServer 5 systems, see ``Configuring interrupt handlers''.

ivect (interrupt vector) table

During system configuration, an ivect[] (interrupt vector) table is generated and initialized with the address of interrupt handlers corresponding to the various hardware interrupts. For example, based on the entries in the sdevice file shown below, the seventh field in the ivect table will be initialized to lpintr(), the address of the interrupt handler provided by the parallel port driver.

sdevice File for the lp Driver

   lp      Y       1       3       1       7       378     37F     0      0      -1
Conceptually, there exists a single ivect[] table. However, a per-processor iplmask[] table and, if proper locking is not provided, critical sections of driver code (base and interrupt) can be executed simultaneously on multiple processors.

Interrupt processing

On most major Intel x86-based systems, hardware device interrupts are routed through a Programmable Interrupt Controller (PIC) before being serviced by the processor. The typical interrupt processing sequence on x86-based platforms proceeds as follows:

  1. A device issues a request for service by signaling the PIC over the interrupt line.

  2. The PIC forwards the request for service to the CPU.

  3. The CPU acknowledges the interrupt.

  4. In turn, the PIC identifies the highest priority interrupt it wishes to be serviced (multiple hardware devices can signal the PIC during the PIC/CPU handshake sequences)

  5. The operating system, with the help of the CPU, translates the PIC's request into an index into the ivect[] table and invokes the corresponding interrupt handler to service the interrupt.

  6. Finally, the kernel issues an End Of Interrupt (EOI) signal indicating that the interrupt handling sequence has completed.

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OpenServer 6 and UnixWare (SVR5) HDK - June 2005