Hardware architecture

The hardware architecture provides several capabilities that are required for multiprocessing. Recent PC hardware architectures include a number of performance enhancements (such as per-processor data/instruction caches, fast memory/CPU bus, and high-speed I/O systems) that were once found only in the large-scale environments of minicomputers and mainframes. SCO multiprocessing systems use the following hardware features:

• The same byte is visible at the same address for all processors, and all memory is accessible by all processors.

• A transparent data/instruction cache that can compensate for the fact that bus and memory speeds are generally slower than processor speeds. A cache reduces bus contention by allowing memory fetches to be completed without requiring the CPU to wait for the bus or for the transfer of data to main memory. Reducing bus contention also allows all the CPUs faster access to the bus when main memory access is required, which improves general system performance. Hardware caches with high hit rates improve both local CPU performance and overall system performance.

• All CPUs can interrupt each other. This is required for priority-based scheduling, optimal clock interrupt servicing, and distributed device driver execution.